In field effect transistor (FET) processing, the replacement of conventional gates, which include a silicon oxide gate dielectric layer and a doped polysilicon gate conductor layer, with replacement metal gates, which include high-K gate dielectric layer(s) and metal gate conductor layer(s), has allowed for device scaling at the 32 nm node and beyond. However, the current techniques used to replace conventional gates with replacement metal gates can lead to gate-to-contact shorts and, more particularly, shorts (also referred to herein as stringers) that occur between a replacement metal gate and the adjacent contacts (also referred to herein as TS contacts or metal plugs) that extend to the FET source/drain regions. Such gate-to-contact shorts can, in turn, lead to device fails, particularly, at high operating voltages (e.g., as evidenced by the results of high voltage stress (HVS) testing).